1. Field of the Invention
The present invention relates generally to the field of computers, and more particularly, to a system and method for implementing a debug mode in a superscalar reduced instruction set computer (RISC) which does not support precise floating point exceptions in its normal mode of operation.
2. Related Art
Superscalar reduced instruction set computers (RISC) (commonly referred to as "RISC processors") are rapidly becoming the new computer architecture for machines for single processor workstations to multiprocessor supercomputers. The MIPS RISC architecture is a specific architecture exemplified by the R2000, R3000, R4000 and R6000 (collectively known as the R series) processors. A book titled, MIPS RISC Architecture by G. Kane and J. Heinrich (Prentice Hall, Englewood Cliffs, N.J., U.S.A., 1992), is the primary reference manual for the MIPS RISC architecture and is incorporated herein by reference.
The following three text books provide further discussions of RISC architecture: John L. Hennessy and David A. Patterson, Computer Architecture--A Quantitative Approach, (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., U.S.A., 1990); Mike Johnson, Superscalar Microprocessor Design, (Prentice Hall, Englewood Cliffs, N.J., U.S.A., 1991); and Stephen B. Furber, VLSI RISC Architecture and Organization, (Marcel Dekker, Inc., New York, N.Y., U.S.A., 1989), all of which are incorporated herein by reference.
All previous MIPS machines have had precise exceptions. Precise exceptions require two necessary conditions: (1) the address of the instruction that caused the exception (the excepting instruction) must be available to the processor or the user, and (2) the processor must be able to return its state back to the state that it was in just prior to the execution of the instruction that caused the exception. That is, if anything goes wrong with an instruction, all previous MIPS processors, for example, recover the state of the processor just before executing that instruction and then transfer program flow to a software handler that can determine what to do with that instruction and the subsequent instruction stream.
The problem with having precise exceptions is that it takes a great deal of hardware in the processor to get back the state just before the excepting instruction is executed. Specifically, more hardware is required to handle precise exceptions as the processors are designed to have more parallelism (performing more operations at the same time).
Some types of exceptions do not need to be precise. If a floating point divide by zero error occurs, for instance, most programs either terminate or run without exception. In neither case is it essential to the correct operation of the program that floating point divide by zero exceptions be precise. On the other hand, very few programs will run correctly with imprecise translation lookaside buffer (TLB) refill exceptions. Thus, a distinction can be made between integer exceptions, which have to be precise, and floating point exceptions, which may not.
What is desired is a processor that provides the parallelism made possible by imprecise floating point exceptions, but still provides precise exceptions to those few older programs that cannot run without them.